Before we discuss Threadripper specifically, let’s recap what we already know about the Zen microarchitecture as it applies to AMD’s new processor lineup.


The most fundamental building block of Zen is the Core Complex, or CCX for short. Each CCX incorporates 4 CPU cores with exclusive L1 and L2 cache as well as a shared pool of L3 cache. Typically each core has 512KB of L2 Cache, whilst the CCX as a whole has 8MB of L3 Cache (2MB per core). Communication between CCX is via a protocol AMD are calling Infinity Fabric, allowing L3 cache to be addressed and accessed by other CCX modules in proximity at a speed proportional to DRAM.

A striking aspect of this architectural design is its inherent scalability. Desktop Ryzen CPUs incorporate two CCX modules on the die (Ryzen dies are individually codenamed Zepplin) for a total of up to 8 CPU cores, and by selectively disabling cores scales down to as few as four active cores, with optional access to the full 16MB L3 cache pool of the whole chip. Later this year Raven Ridge APUs will likely feature just one CCX alongside a graphics module, communicating via Infinity Fabric. But Zen scalability can go beyond this.


Zen CPU cores also support Simultaneous Multithreading. A technique similar to Intel’s Hyperthreading, SMT allows one core to work on two quasi-independent tasks or threads of execution at the same time, garnering time savings by sharing resources and efficient scheduling so workload isn’t duplicated. Each Zepplin die can support up to 16 threads, a far cry from the maximum of eight on Intel’s Core i7-7700K.


AMD’s EPYC server CPUs incorporate four Zepplin dies per CPU package, for a total of 32 CPU cores. Communication between dies is once again via Infinity Fabric, allowing a die can access system memory normally only directly addressable by another die. Each die acts as a NUMA (non-uniform memory access) node addressing memory through two DDR4 memory channels, and as a consequence single-socket EPYC solutions support up to eight DDR4 memory channels.

Intel by contrast utilise single monolithic cores for their CPU designs. These have a number of practical benefits, the most obvious of which is that cross-core communication isn’t limited in speed in the same way that Infinity Fabric limits Ryzen. There is a trade-off however: Die Size.

Rather than using two or more discrete CPU dies Intel’s designs are ‘monolithic’ – they manufacture a single die, and then disable cores to determine SKU. The larger the die, the lower the manufacturing yield (effective number of usable CPUs printed per wafer) and higher costs of production will be. Intel Xeon CPUs utilising the Skylake X architecture may feature more than 20 cores (the HEDT Core i9-7950X tops out at 18 cores, but is derived from those Xeon parts) but on one die alone. By using a modular approach to manufacture and creating only smaller 8-core Zepplin dies, it’s theorised that AMD is reducing production costs on EPYC and Threadripper significantly.

SenseMI Technology

Modern CPUs are extremely complex structures which dynamically respond to the workloads placed upon them. That’s not a simple process – sensor data for temperatures, voltages and more is continually analysed in parallel to workloads, and algorithms have been designed which balances the load and overclocks cores beyond a base where headroom allows.

The sensor structures and back-end required for this has become complex in its own right, and AMD are using SenseMI Technology as an umbrella term for this on-CPU functionality. AMD break it down into five distinct facets:



A deeper discussion of AMD’s Zen architecture beyond the scope of this review is available at Wikichip.