What kind of Performance Can We Eventually Expect?

Whilst I’m sure many have heard of the previous experiments of cluster based processing experiments like the 80 core CPU from Intel?



The 80 cores were experimental and are nowhere near as comprehensive as contemporary CPUs, it is likely that these experiments inspired future (current?) and beyond CPU designs. Does this mean that we should expect mega cluster processing units in future?
Say for example, we scale down a 32nm i7 2600K with a die size of 216mm² with 995,000,000 transistors.
@ 2nm in the same die space we could fit in direct translation (its more complicated that direct scale down mind.) approximately 255,000,000,000, which is about 256 times more transistors.
(An issue with this conversion is that the i7 2600k has used about 20-30% of die space on GPU. Due to the architectural differences in GPU and CPU there is likely to be difference in concentrations of CPU transistors and GPU transistors etc. This conversion isn’t meant to be accurate, just to highlight how vast the difference between 32-2nm is.)
Regardless will this mean that we can expect CPUs with hundreds of cores come 2nm fabrication? Or will the implementation of new architecture with larger more complex cores arrive while sticking to <100 cores per die?

By Moore’s law, we are only 5 generations away till 2nm @ 18months per Gen.
• 22nm- 2012-2013
• 14nm- 2013-2015
• 10nm- 2015-2017
• 6nm- 2017-2019
• 2nm- 2020> ?

We are likely only to be around 10 years at most away from 2nm fabrication, technology dependant.

If we assume 15% performance increase per generation +10% per new architecture, can we expect that with 2nm fabrication that we may get a 128 cored CPU with 256 threads that are 160-200% better than Sandy Bridge per core?

I’m sure the scaling and architecture changes will be different from those numbers but it does give basic insight to where we are heading in future. This doesn’t include utilisation of GPU cores, which is definitely going to happen which will bring more performance benefits in highly parallel workloads and floating point calculations. But once we are at 2nm fabrication, performance will only be dictated by die size and microprocessor design.

By moving into 3D space, die size and design potentials can be vastly expanded.